GDA's DDR2/3 memory controller is a highly efficient and configurable design targeted for bandwidth hungry applications like DSP processors, Video codec, graphics and general interfaces.
The controller is simple and configurable. Its layered architecture is independent of application logic, PHY designs, implementation tools and most importantly the target technology.
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GDA Memory controller maximizes channel bandwidth and minimizes access latencies through efficient request scheduling, intelligent refresh schemes, flexible page management policies and configurable address mapping schemes.
Optional support for multiple agents is provided with configurable Quality of Service for agents.
GDA Memory controller provides support for all defined low power states of the memory. Optionally it can be configured to manage power mode transitions of the memory, PHY and controller for aggressive power savings.
The memory controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP-IP etc.
Specifications
Configurable Options
- Memory Support - DDR2, DDR3 or Combo Controller
- Memory Capacity Support - Up to 32 GB
- Memory Channel Widths - x8/x16/x32/x64
- Number of ranks - 1 to 4
- Page Management Policy - Closed/Open Page
- Address Mapping Schemes
- Number of Ports - 1 to 16
- QoS Policy for Ports
- Power Management
Design Attributes
- Synthesizable Verilog RTL
- Verilog Test Environment with performance monitors and Test Cases
- Synthesis Scripts
- Documentation
Product Package
- Configurable RTL Code
- Verilog Test Environment with performance monitors
- Test cases
- Configurable synthesis shell
Availability: Now
Features:
- Compliant with JEDEC DDR2/3
Standards (400-800MHz/800-1333 MHz)
- Pin strap/register option to support
DDR2 or DDR3
- Pipeline architecture to increase
operational efficiency
- Single Port support with configurable
command queue size
- Optional Multiple port support with programmable
arbitration policies
- Flexible and programmable address mapping
- Support for open and close page policies
- Support for various power states - Self
Refresh, Active Power Down, Pre-charge Power Down
- Programmable timing parameters for RCD,
RP, RFC, FAW, CCD,WR,RTP,RRD, MRD,WL,DAL
- Supports On-Die-Termination, Leveling, Calibration
- Compliant with Denali PHY I/F (DFI) specifications
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