The MIPI Camera Serial Interface 2 (CSI-2) specification defines an interface between a peripheral device (camera) and a host processor (baseband, application engine). This interface is defined by MIPI consortium, which defines a series of modules in a MIPI compliant product.
Click here to view the block diagram
GDA MIPI CSI receiver is used in mobile and high-speed serial applications where a camera can send the video data using MIPI CSI Transmitter over MIPI lines to the MIPI CSI Receiver for decoding the data and use it for subsequent processing. MIPI CSI Receiver adheres to MIPI CSI Specification. The GDA MIPI CSI Receiver along with GDA MIPI DPHY provides a complete solution for decoding MIPI data.
Design Attributes
- Highly modular design
- Fully synchronous design
- Active low Asynchronous reset
Product Package
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
Documentation
- Design Guide
- Synthesis guide
Availability : Now
Language: Verilog HDL
Synthesis : Design Compiler
FPGA: Xilinx ISE on Virtex5
Simulation: Modelsim, Verilog NC
GDA Technologies Inc. (An L&T Infotech Company) is a leading Electronic Design Services (EDS) and Silicon Intellectual Property (SIP) solution provider for the Embedded, Networking, and Consumer Electronics Markets. GDA is focused on designing IC and board level products from concept to implementation. GDA has successfully developed products in areas of high-speed communications, Digital Video, Internet Appliances, and Mobile Solutions.
Features:
- Compliant with MIPI CSI Spec v1.01.00 Rev 0.03 and MIPI D-PHY Spec v0.9
- Programmable 1, 2 or 4 Data Lane Configuration
- Operate in continuous and non-continuous clock modes
- Command and Video Mode (Burst and Non-Burst mode) support
- Video Stream Packet Formats: YUV 422 8-bit, RGB888, RGB565, RAW8, RAW10, RAW12
- Progressive Scanning
- Camera Interface: 8, 16 and 24 bit per pixel
- Data Rate: 800 Mbps per lane on silicon (Spec mentions a max of 500 Mbps per lane)
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