GDA complete Switch for PCI Express™
Serial Link Interface
PCI Express Switch
A PCI Express switch provides fan-out capability and enables a series of connectors for add-in, high performance I/Os. PCIe switches allow limited north bridge resources to be distributed to multiple I/O end points and enable efficient use of available bandwidth.
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The GDA® PCI Express Switch solution is a complete full functional PCI Express switch consisting of the switch core and the switch port controllers and implements the entire switch functionality like packet routing, interrupt, configuration access, power management and error reporting functions.
Superior Architecture
The GDA PCI Express Switch IP uses non blocking architecture and provides very high bandwidth and low latency. The architecture is also optimized for lower power consumption, and silicon footprint.
The GDA PCI Express Switch IP offers maximum off-load through the hardware logic and a high degree of dynamic programmability. This solution provides highly scalable bandwidth through configurable link width, data path width and clock frequency. Most Thoroughly Verified and Interoperable Design.
The GDA PCI Express Switch is an exhaustively verified solution and is fully tested against design specific and protocol compliance checklist. The comprehensive directed and random tests ensures a very high coverage. The IP is verified with leading PCIe verification IP’s and the verification environment can be configured to run with all the major simulators. The reusable block level verification environment and the formal verification methodology enhance the quality of verification process and add more confidence to the design verification.
The GDA PCI Express-Switch solution leverages years of experience in creating reusable IP for Ethernet, RapidIO and PCI Express technologies. The expertise in creating those system validated solutions with RTL, synthesis, simulation, board and software ensures delivery of lower risk, compliant and interoperable solution
Ease of Integration
The GDA PCI Express Switch design is fully synchronous and adheres to standard synthesis, test insertion and physical design practices. The solution allows licensees to easily migrate among COT, FPGA, Gate array, structured ASIC and Standard cell technologies. The IP with its flexible user logic interface can be easily integrated into a wide range of applications.
Superior Comprehensive Support
The GDA PCI Express Switch solution comes with a superior support model that offers round the clock telephone, email, web based support and free code updates during the support period. Support documents including a data sheet, verification guide, synthesis guide and application notes are also offered. To build a full-system solution the GDA partner eco-system provides access to additional components such as verification IP, PHYs and related design services.
Design Configurability
The design offers enormous hardware and software configurable options allowing the user to choose the optimal solution to meet his requirement. The configuration options include
- Number of downstream ports
- User Logic Interface to suit specific application
- Maximum link width supported (x1, x2, x4, x8, x16)
- 8/16 bit PIPE interface
- Data path width (64 or 128 bits)
- System clock frequency
- Include/exclude Receive Buffer
- Number of Virtual Channels
- VC Arbitration scheme
- Port Arbitration scheme
- ECRC generation and checking
- Receive Buffer size and Retry Buffer size for each port
- Exclusion of any optional feature
- Implementation specific registers
- Synchronous/Asynchronous reset
Deliverables
The deliverables include
- Verilog RTL
- Behavioral test bench and test cases
- PCI Express and Application BFM
- ASIC Synthesis environment
- Documentation
Features:
- Compliant with PCI Express Base 1.1 or 2.0
Specifications
- Complete solution with upstream /downstream
switch ports and the switch interconnect
- Highly configurable: Support for
x1, x4, x8, x16-lane implementations
- 5Gbps data rate per lane in Gen 2 mode
- Internal data path width: 64 or 128 bits
- TLP data payload size from 128 B to 4 KB
- Ability to configure the features of each switch
port independently
- Non blocking architecture for high link utilization
and low latency
- Parallel address decoding for all egress ports
- Support for integrated Endpoints within the switch
- Up to 8 virtual channels
Debug and Test Features
The solution provides comprehensive debug and
test features such as
- Implementation specific registers for debugging
- Comprehensive error reporting
- Multiple loopback modes
Power Management Features
The design supports mandatory and most
of the optional power management features
such as
- L0, L0s, L1, L2 power management states,
beacon, PME and auxiliary power
- Full PCI-PM and ASPM Support for L0s, L1
Configuration Features
This solution implements the configuration
space and implementation specific control and status
registers to address the following functionality
- Configuration and message transactions handled
internally
- Configuration access to internal ports and
type-1/type-0 conversion for configuration
transactions targeted to downstream devices
- Supports all optional configuration space
capability structures
- Implementation specific registers for each port
- Peripheral interface for register access
- Exhaustive Control, Status and Debug registers
- Support for link reconfiguration, programmablelink width on multi-lane ports
- Advanced Error reporting
- Efficient buffering scheme for Retry buffer
and receive buffer
- Completely handles PCI Express ordering
rules and flow control
- INTX, MSI interrupt support
- Round Robin, Strict Priority and WRR
support for VC arbitration for Port Arbitration
- Option to connect an integrated/embedded
Endpoint to any Downstream Port without PCIe Link
- Unsupported request and unexpected
completion handling for both upstream
and downstream traffic
- Lane ordering and reversal
- Isochronous transfers supported
- Flexible lane ordering and support for lane reversal
- Supports ARI Forwarding
- Optional packet buffer and scheduler modules
- Supports configurable number of downstream ports
- Supports parallel address decoding
- Handling of UR for both upstream and downstream
traffic
Applications
- PC's workstations and servers
- Storage
- Networking and communications
- Switches and routers
- General purpose system chip interconnect for any compute platform
Benefits
- Superior architecture-optimized for high performance, link utilization, low latency, low power and low gate count
- Feature rich, highly flexible, scalable, configurable and timing friendly design
- Ease of integration
- Verified with leading VIP
*PCI Express is a registered trademark of the PCI-SIG. GDA (An L&T Infotech Company) IP; Sold under GDA’s Re-seller agreement with Rambus, Inc.
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